With the increasing scope of data transmissions and the increasing clock frequencies of computers, circuits which have a relatively high bandwidth are needed. In integrated output driver circuits, the usable bandwidth is usually limited by parasitic capacitances, such as by parasitic capacitances in a data output connection (pad), and by inductances in an output line (bondwire) which is normally connected to the pad.
To increase the bandwidth, the prior art involves attempts to keep the parasitic capacitances as small as possible, since this makes it possible to achieve an increase in the available bandwidth. Circuit arrangements based on the prior art are designed using CML technology, inter alia An MOS Current Mode Logic (MCML) Circuit for Low-Power GHz Processors, M. Yamashina and H. Yamada, NEC Res. & Develop., 36, No. 1 (1995), pp. 54-62.
A second approach to increasing the available bandwidth based on the prior art is to use “peaking coils” 40-Gb/s High-Power Modulator Driver IC for Lightwave Communication Systems, Z. Lao et al., IEEE Journal of Solid-State Circuits, 33, No. 10 (1998), pp. 1520-1526. Peaking coils are coils (inductances) which are arranged in the power supply part of an output circuit. As when designing a circuit to have the smallest possible parasitic capacitances, these increase the usable bandwidth of an output circuit. A schematic output circuit in a differential amplifier having integrated peaking coils based on the prior art is shown in FIG. 7.
FIG. 7 illustrates an equivalent circuit diagram of an integrated circuit arrangement 50 based on the prior art which has a differential amplifier 51 as an output stage. A first data input 1 on the differential amplifier 51 is coupled to the gate of a first transistor 2, whose first source/drain region is coupled to a first node 3 and whose second source/drain region is coupled to a second node 4. The second node 4 forms a first output connection on the differential amplifier 51. The first node 3 is coupled to a connection on a current source 5 and to a first source/drain region of a second transistor 6. The gate of the second transistor 6 is coupled to a second data input 7, which second data input is differential with respect to the first data input 1. The second source/drain region of the second transistor 6 is coupled to a third node 8. The third node 8 forms a second output connection on the differential amplifier 51. The second node 4 is coupled to a first peaking coil 9 and to a first line 10, which forms a first line 10 from the first output connection 4 of the differential amplifier 51 to a first data output connection (pad) 52. The first peaking coil 9 is also coupled to a connection on a voltage source 53 by means of a first resistor 11. The third node 8 is coupled to a second peaking coil 12 and to a second line 13, which forms a second line 13 from the second output connection 8 of the differential amplifier 51 to a second data output connection (pad) 54. The second peaking coil 12 is also coupled to the second connection of the voltage source by means of a second resistor 14.
The first output connection 4 of the differential amplifier 51 is coupled to a fourth node 15. The fourth node 15 is coupled to a first capacitance 16, which essentially represents the parasitic capacitances of the output circuit (transistor 2). In addition, the fourth node 15 is coupled to a fifth node 17. The fifth node 17 is coupled to a second capacitance 18, which essentially represents the parasitic capacitances of the first data output connection 52. In addition, the fifth node 17 is coupled to a first data output 19.
The second output connection 8 of the differential amplifier 51 is coupled to a sixth node 20. The sixth node 20 is coupled to a third capacitance 21, which essentially represents the parasitic capacitances of the output circuit (transistor 6). In addition, the sixth node 20 is coupled to a seventh node 22. The seventh node 22 is coupled to a fourth capacitance 23, which essentially represents the parasitic capacitances of the second data output connection 54. In addition, the seventh node 22 is coupled to a second data output 24.
Even when using peaking coils, however, the parasitic capacitances of the data output connections 52, 54 cause a reduction in the usable bandwidth to a value below the intrinsic bandwidth of the circuit. That is to say that the usable bandwidth of the circuit is smaller than would be achievable with the type of components which is used if no parasitic capacitances were to arise.
DE 696 16 126 T2 discloses a method for stabilizing a power converter in the face of oscillations which are caused by mismatches between the setting value for an output voltage and an available large number of quantized work cycles.
DE 28 09 498 C2 discloses an operation monitoring system for radar installations with a monitoring reception device (situated close to the radar antenna) for obtaining a sample of the transmitted signal from the radar transmitter.
There is a need to increase the available bandwidth in an output circuit. For these and other reasons, there is a need for the present invention.